1. Field of the Invention
This invention relates to a pipelined multiple issue packet switch.
2. Description of Related Art
When computers are coupled together into networks for communication, it is known to couple networks together and to provide a switching device which is coupled to more than one network. The switching device receives packets from one network and retransmits those packets (possibly in another format) on another network. In general, it is desirable for the switching device to operate as quickly as possible.
However, there are several constraints under which the switching device must operate. First, packets may encapsulate differing protocols, and thus may differ significantly in length and in processing time. Second, when switching packets from one network to another, it is generally required that packets are re-transmitted in the same order as they arrive. Because of these two constraints, known switching device architectures are not able to take advantage of significant parallelism in switching packets.
It is also desirable to account ahead of time for future improvements in processing hardware, such as bandwidth and speed of a network interface, clock speed of a switching processor, and memory size of a packet buffer, so that the design of the switching device is flexible and scaleable with such improvements.
The following U.S. Patents may be pertinent:
U.S. Pat. No. 4,446,555 to Devault et al., "Time Division Multiplex Switching Network For Multiservice Digital Networks"; PA1 U.S. Pat. No. 5,212,686 to Joy et al., "Asynchronous Time Division Switching Arrangement and A Method of Operating Same"; PA1 U.S. Pat. No. 5,271,004 to Proctor et al., "Asynchronous Transfer Mode Switching Arrangement Providing Broadcast Transmission"; and PA1 U.S. Pat. No. 5,307,343 to Bostica et al., "Basic Element for the Connection Network of A Fast Packet Switching Node".
Accordingly, it would be advantageous to provide an improved architecture for a packet switch, which can make packet switching decisions responsive to link layer (ISO level 2) or protocol layer (ISO level 3) header information, which is capable of high speed operation at relatively low cost, and which is flexible and scaleable with future improvements in processing hardware.